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TRF1121
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TERMINAL FUNCTIONS
TRF1221
SLWS170B – APRIL 2005 – REVISED JANUARY 2008
TERMINAL
NAME NO.
I/O
TYPE
DESCRIPTION
BBIN
BBIP
21
22
I
I
Analog Baseband IF input (2-k ? differential) negative, dc-coupled; internal voltage is 4 V DC
Analog Baseband IF input (2-k ? differential) positive, dc-coupled; internal voltage is 4 V DC
CLK
5
I
Digital
Serial interface clock input
CP1O
CP2O
13
1
O
O
Analog Analog synthesizer 1 charge pump output
Analog Analog synthesizer 2 charge pump output
DATA
EN
4
10
I
I
Digital
Digital
Serial interface data input
Serial interface load enable (active-high)
EXTLO2IN
EXTLO2IP
FR
FRBP
35
36
7
9
I
I
I
O
Analog External input for LO2 (differential) negative and logic level for VCO select.
Analog External input for LO2 (differential) positive and logic level for VCO select.
Analog 18-MHz reference clock input, HCMOS input. (DC level = 2.5 V)
Analog Reference frequency bypass. Internally biased to 2.5 V.
GAIN[0]
GAIN[1]
GAIN[2]
GAIN[3]
GAIN[4]
GND
24
25
26
27
28
18–20, 29, 30,
I
I
I
I
I
Digital
Digital
Digital
Digital
Digital
Power
Gain control bit 0 (LSB). Logic low induces 1-dB attenuation.
Gain control bit 1. Logic low induces 2-dB attenuation.
Gain control bit 2. Logic low induces 4-dB attenuation.
Gain control bit 3. Logic low induces 8-dB attenuation.
Gain control bit 4 (MSB). Logic low induces 16-dB attenuation.
Ground
37, 39, 42
IFON
IFOP
31
33
O
O
Analog IF analog output (100- ? differential) negative, dc-coupled, internal voltage is 2.1 V dc.
Analog IF analog output (100- ? differential) positive, dc-coupled, internal voltage is 2.1 V dc.
LD1
LD2
12
2
O
O
Digital
Digital
Synthesizer 1 lock detect output, high is locked.
Synthesizer 2 lock detect output, high is locked.
LF1
LF2
LO1BPA
11
3
14
O
O
O
Analog Lock detect filter capacitor for LO1, 0.01 μ F typical 100 k ? (1)
Analog Lock detect filter capacitor for LO2, 0.01- μ F typical, 100-k ? pullup (1)
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
LO1BPB
LO1TUN
LO2ABPA
16
15
46
O
I
O
Analog Bypass capacitor for LO1, 0.1 μ F (min), DCV = 1 V
Analog VCO synthesizer 1 tuning port
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
LO2ABPB
LO2ATUN
LO2BBPA
48
47
43
O
I
O
Analog Bypass capacitor for LO2A, 0.1 μ F (min), DCV = 1 V
Analog LO2A tune port
Analog Not connected for normal operation. DC bias nominal 1.8 V. Do not ground or connect to
any other pin.
LO2BBPB
LO2BTUN
LO2ON
LO2OP
45
44
40
41
O
I
O
O
Analog Bypass capacitor for LO2B, 0.1 μ F (min), DCV = 1 V
Analog LO2B tune port
Analog LO2 negative output (differential) and positive VCC bias (5 V) for LO buffer amplifier
Analog LO2 positive output (differential) and positive VCC bias (5 V) for LO buffer amplifier
TXON
VCCD1
VCCD2
VCCIF
VCCLO1
VCCLO2
VCCUPC
34
8
6
32
17
38
23
I
I
I
I
I
I
I
Digital
Power
Power
Power
Power
Power
Power
IF amplifier enable active high
5-V power for digital
5-V power for digital
5-V power for analog
VCC for LO1
VCC for LO2 A and B
5-V power for analog
Back
Back side of package has metal base that must be grounded for thermal and RF performance
(1)
Current leakage on the order of 10 μ A through the capacitor or by any other means from either LF pin can cause false loss-of-lock
signals. The two pullup resistors (R16 and R17) in Figure 23 reduce this sensitivity.
Copyright ? 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): TRF1121 TRF1221
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